In recent years, it has become important to reduce power consumption of semiconductor integrated circuit devices. Importance is attached to reduction of a supply voltage so as to reduce the power consumption. Then, in order to increase processing capability even if the supply voltage is reduced, the substrate back bias for the semiconductor integrated circuit device is controlled. The substrate back bias is a weak back bias voltage to be applied to a well formed in a substrate for a transistor. When the transistor is operated, the substrate back bias is applied in a forward direction to facilitate flow of a current through a channel of the transistor. The transistor is thereby operated at a low voltage, and the faster operation is achieved. On the other hand, when the transistor is stopped, the substrate back bias in the forward direction is not applied, thereby reducing current leakage.
The substrate back bias is supplied through wires for substrate back-bias control, disposed aside from wires for ordinary substrate bias control. A description will be given to conventional wires in a semiconductor integrated circuit for supplying the bias, by using drawings. FIG. 2A is a partial plan view and FIG. 2B is a partially enlarged sectional view taken along a line Y-Y′, both schematically showing a wiring structure for supplying the bias to a semiconductor integrated circuit device according to a prior art.
In a semiconductor integrated circuit device 101, on a deep N well 103 in a P-type substrate 102, P wells 104 and N wells 105 are formed in the form of strips, respectively. In an interlayer insulating film 108 on the P wells 104, substrate bias controlling GND wires 112 are formed in a direction in which the P wells 104 extend. In the interlayer insulating film 108 on the N wells 105, substrate bias controlling VDD wires 111 are formed in a direction in which the N wells 105 extend. On the interlayer insulating film 108 above the substrate bias controlling VDD wires 111 and the substrate bias controlling GND wires 112, a substrate back-bias controlling VDD wire 113 and a substrate back-bias controlling GND wire 114 that three-dimensionally intersect with the substrate bias controlling VDD wires 111 and the substrate bias controlling GND wires 112 are formed. In each N well 105 in the vicinity of a point at which a substrate bias controlling VDD wire 111 three-dimensionally intersects with the substrate back-bias controlling VDD wire 113, an N+ diffusion layer 107 is formed. In each P well 104 in the vicinity of a point at which a substrate bias controlling GND wire 112 three-dimensionally intersects with the substrate back-bias controlling GND wire 114, a P+ diffusion layer 106 is formed. The substrate back-bias controlling VDD wire 113 is electrically connected to N+ diffusion layers 107 through via contacts 115, while the substrate back-bias controlling GND wire 114 is electrically connected to P+ diffusion layers 106 through via contacts 116. Signal lines 117 electrically connected to transistors (not shown) are formed in the interlayer insulating film 108 between the substrate back-bias controlling VDD wire 113 and the substrate back-bias controlling GND wire 114, above the substrate bias controlling VDD wires 111 and the substrate bias controlling GND wires 112. Since a potential difference between the substrate back-bias controlling wires 113 and 114 and the signal lines 117 is large, a predetermined interval is secured between the substrate back-bias controlling wires 113 and 114 and the signal lines 117.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-61-196617